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CY15B102Q 2-mbit (256 k 8) serial (spi) automotive f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-89166 rev. *f revised april 20, 2017 2-mbit (256 k 8) serial (spi) automotive f-ram features 2-mbit ferroelectric random a ccess memory (f-ram) logically organized as 256 k 8 ? high-endurance 10 trillion (10 13 ) read/writes ? 121-year data retention (see the data retention and endurance table) ? nodelay? writes ? advanced high-reliability ferroelectric process very fast serial peripheral interface (spi) ? up to 25 mhz frequency ? direct hardware replacement for serial flash and eeprom ? supports spi mode 0 (0, 0) and mode 3 (1, 1) sophisticated write protection scheme ? hardware protection using the write protect (wp ) pin ? software protection using write disable instruction ? software block protection for 1/4, 1/2, or entire array device id ? manufacturer id and product id low power consumption ? 5 ma active current at 25 mhz ? 750 ? a standby current ? 20 ? a sleep mode current low-voltage operation: v dd = 2.0 v to 3.6 v automotive-e temperature: ?40 ? c to +125 ? c 8-pin small outline integrated circuit (soic) package aec q100 grade 1 compliant restriction of hazardous substances (rohs) compliant functional overview the CY15B102Q is a 2-mbit no nvolatile memory employing an advanced ferroelectric process. f-ram is nonvolatile and performs reads and writes similar to a ram. it provides reliable data retention for 121 years while eliminating the complexities, overhead, and system-level reliab ility problems caused by serial flash, eeprom, and other nonvolatile memories. unlike serial flash and eeprom, the CY15B102Q performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product offers substantial writ e endurance compared with other nonvolatile memories. the CY15B102Q is capable of supporting 10 13 read/write cycles, or 10 millio n times more write cycles than eeprom. these capabilities make the cy 15b102q ideal for nonvolatile memory applications requirin g frequent or rapid writes. examples range from data collec tion, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash or eeprom can cause data loss. the CY15B102Q provides substantial benefits to users of serial eeprom or flash as a hardware drop-in replacement. the CY15B102Q uses the high-speed spi bus, which enhances the high-speed write capability of f-ram technology. the device incorporates a read-only device id that allows the host to determine the manufacturer, product density, and product revision. the device specific ations are guaranteed over an automotive-e temperature range of ?40 ? c to +125 ? c. logic block diagram instruction decoder clock generator control logic write protect instruction register address register counter 256 k x 8 f-ram array 18 data i/ o register 8 nonvolatile status register 3 wp cs hold sck so si
CY15B102Q document number: 001-89166 rev. *f page 2 of 22 contents pinout ................................................................................ 3 pin definitions .................................................................. 3 overview............................................................................ 4 memory architecture........................................................ 4 serial peripheral interface - spi bus .............................. 4 spi overview............................................................... 4 spi modes................................................................... 5 power up to first access ........ .................................... 6 command structure .................................................... 6 wren - set write enable latch .............. .............. ..... 6 wrdi - reset write enable latch............................... 6 status register and write prot ection ............................. 7 rdsr - read status register. .................................... 7 wrsr - write status register .................................... 7 memory operation............................................................ 8 write operation ........................................................... 8 read operation ........................................................... 8 fast read operation ................................................... 8 hold pin operation ................................................. 10 sleep mode ............................................................... 10 device id................................................................... 11 endurance ................................................................. 11 maximum ratings........................................................... 12 operating range............................................................. 12 dc electrical characteristics ........................................ 12 data retention and endurance ..................................... 13 example of an f-ram life time in an aec-q100 automotive application............................... 13 capacitance .................................................................... 13 thermal resistance........................................................ 13 ac test conditions ........................................................ 13 ac switching characteristics ....................................... 14 power cycle timing ....................................................... 16 ordering information...................................................... 17 ordering code definitions ...... ................................... 17 package diagrams.......................................................... 18 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 22 worldwide sales and design supp ort............. .......... 22 products .................................................................... 22 psoc? solutions ...................................................... 22 cypress developer community................................. 22 technical support .................. ................................... 22
CY15B102Q document number: 001-89166 rev. *f page 3 of 22 pinout figure 1. 8-pin soic pinout hold sck 1 2 3 4 5 cs 8 7 6 v dd si so top view not to scale v ss wp pin definitions pin name i/o type description sck input serial clock . all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. because the device is synchronous, the clock frequency may be any value between 0 and 25 mhz and may be interrupted at any time. cs input chip select . this active low input activates the device. when high, the device enters the low-power standby mode, ignores other inputs, and the output is tristated. when low, the device internally activates the sck signal. a falling edge on cs must occur before every opcode. si [1] input serial input . all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it s hould always be driven to a valid logi c level to meet idd specifications. so [1] output serial output . this is the data output pin. it is driven during a read and remains tristated at all other times including when hold is low. data transitions are driven on the falling edge of the serial clock. wp input write protect . this active low pin prevents write operati on to the status register when wpen is set to ?1?. this is critical because other write protecti on features are controlled th rough the status register. a complete explanation of wr ite protection is provided on status register and wr ite protection on page 7 . this pin must be tied to v dd if not used. hold input hold pin . the hold pin is used when the host cpu must interrupt a memory operation for another task. when hold is low, the current operation is suspended. the device ignores any transition on sck or cs . all transitions on hold must occur while sck is low. this pin must be tied to v dd if not used. v ss power supply ground for the device. must be connected to the ground of the system. v dd power supply power supply input to the device. note 1. si may be connected to so for a single-pin data interface .
CY15B102Q document number: 001-89166 rev. *f page 4 of 22 overview the CY15B102Q is a serial f-ram memory. the memory array is logically organized as 262,144 8 bits and is accessed using an industry-standard serial pe ripheral interface (spi) bus. the functional operation of the f-ram is similar to serial flash and serial eeproms. the major difference between the CY15B102Q and a serial flash or eeprom with the same pinout is the f-ram's superior write performance, high endurance, and low power consumption. memory architecture when accessing the CY15B102Q, the user addresses 256k locations of eight data bits each. these eight data bits are shifted in or out serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an opcode, and a three-byte address. the upper 6 bits of the address range are 'don't care' values. the complete address of 18 bits specifies each byte address uniquely. most functions of the CY15B102Q are either controlled by the spi interface or are handled by on-board circuitry. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike a serial flash or eeprom, it is not necessary to poll the device for a ready condition because writes occur at bus speed. by the time a new bus transaction can be shifted into the device, a write operation is complete. this is explained in more detail in the interface section. serial peripheral in terface - spi bus the CY15B102Q is a spi slave device and operates at speeds up to 25 mhz. this high-speed serial bus provides high-perfor- mance serial communication to a spi master. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the CY15B102Q operates in spi modes 0 and 3. spi overview the spi is a four-pin inte rface with chip select (cs ), serial input (si), serial output (so), a nd serial clock (sck) pins. the spi is a synchronous serial interface, which uses clock and data pins for memory access a nd supports multiple devices on the data bus. a device on the spi bus is activated using the cs pin. the relationship between chip select, clock, and data is dictated by the spi mode. this device supports spi modes 0 and 3. in both of these modes, data is clocked into the f-ram on the rising edge of sck starting from the first rising edge after cs goes active. the spi protocol is controlled by opcodes. these opcodes specify the commands from the bus master to the slave device. after cs is activated, the first byte transferred from the bus master is the opcode. followin g the opcode, any addresses and data are then transferred. the cs must go inactive after an operation is complete and before a new opcode can be issued. the commonly used terms in the spi protocol are as follows: spi master the spi master device controls the operations on a spi bus. an spi bus may have only one master with one or more slave devices. all the slaves share the same spi bus lines and the master may select any of t he slave devices using the cs pin. all of the operations must be initiated by the master activating a slave device by pulling the cs pin of the slave low. the master also generates the sck and a ll the data transmission on si and so lines are synchronize d with this clock. spi slave the spi slave device is activated by the master through the chip select line. a slave device gets the sck as an input from the spi master and all the communicat ion is synchronized with this clock. an spi slave never initiates a communication on the spi bus and acts only on the instruction from the master. the CY15B102Q operates as an spi slave and may share the spi bus with other spi slave devices. chip select (cs ) to select any slave device, the master needs to pull down the corresponding cs pin. any instruction can be issued to a slave device only while the cs pin is low. when the device is not selected, data through the si pin is ignored and the serial output pin (so) remains in a high-impedance state. note a new instruction must begin with the falling edge of cs . therefore, only one opcode can be issued for each active chip select cycle. serial clock (sck) the serial clock is generated by the spi master and the communication is synchronize d with this clock after cs goes low. the CY15B102Q enables spi modes 0 and 3 for data commu- nication. in both of these modes, the inputs are latched by the slave device on the rising edge of sck and outputs are issued on the falling edge. therefore, the first rising edge of sck signifies the arrival of the first bit (msb) of a spi instruction on the si pin. further, all data inputs and outputs are synchronized with sck. data transmission (si/so) the spi data bus consists of two lines, si and so, for serial data communication. si is also referred to as master out slave in (mosi) and so is referred to as master in slave out (miso). the master issues instructions to t he slave through the si pin, while the slave responds through the so pin. multiple slave devices may share the si and so lines as described earlier. the CY15B102Q has two separate pi ns for si and so, which can be connected with the master as shown in figure 2 .
CY15B102Q document number: 001-89166 rev. *f page 5 of 22 for a microcontroller that has no dedicated spi bus, a general-purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si and so) together and tie off (high) the hold and wp pins. figure 3 shows such a configuration, which uses only three pins. most significant bit (msb) the spi protocol requires that the first bit to be transmitted is the most significant bit (msb). this is valid for both address and data transmission. the 2-mbit serial f-ram requires a 3-byte address for any read or write operation. because the address is only 18 bits, the first six bits that are fed in are ignored by the device. although these six bits are ?don?t care?, cypr ess recommends that these bits be set to 0s to enable seamless transition to higher memory densities. serial opcode after the slave device is selected with cs going low, the first byte received is treated as the opcode for the intended operation. CY15B102Q uses the standard opcodes for memory accesses. invalid opcode if an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin until the next falling edge of cs , and the so pin remains tristated. status register CY15B102Q has an 8-bit status r egister. the bits in the status register are used to configur e the device. these bits are described in table 3 on page 7 . spi modes CY15B102Q may be driven by a microcontroller with its spi peripheral running in either of the following two modes: spi mode 0 (cpol = 0, cpha = 0) spi mode 3 (cpol = 1, cpha = 1) for both these modes, the input data is latched in on the rising edge of sck starting from the first rising edge after cs goes active. if the clock starts from a high state (in mode 3), the first rising edge after the clock toggles is considered. the output data is available on the falling edge of sck.the two spi modes are shown in figure 4 on page 6 and figure 5 on page 6 . figure 2. system configuration with spi port figure 3. system configuration without spi port cs1 cs2 hold1 hold2 CY15B102Q CY15B102Q wp1 wp2 sck si so sck si so cs hold wp cs hold wp sck mosi miso spi microcontroller CY15B102Q microcontroller sck si so cs hold wp p1.2 p1.1 p1.0
CY15B102Q document number: 001-89166 rev. *f page 6 of 22 the status of the clock when th e bus master is not transferring data is: sck remains at 0 for mode 0 sck remains at 1 for mode 3 the device detects the spi mode from the status of the sck pin when the device is selected by bringing the cs pin low. if the sck pin is low when the device is selected, spi mode 0 is assumed and if the sck pin is high, it works in spi mode 3. power up to first access the CY15B102Q is not accessible for a t pu time after power-up. users must comply with the timing parameter t pu , which is the minimum time from v dd (min) to the first cs low. command structure there are nine commands, call ed opcodes, that can be issued by the bus master to the cy 15b102q. they are listed in table 1 . these opcodes control the functions performed by the memory. wren - set write enable latch the CY15B102Q will power up wit h writes disabled. the wren command must be issued before any write operation. sending the wren opcode allows the user to issue subsequent opcodes for write operations. these include writing the status register (wrsr) and writing the memory (write). sending the wren opcode causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. we l = ?1? indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit - only the wren opcode can set this bit. the wel bit will be automatically cleared on the rising edge of cs following a wrdi, a wrsr, or a write operation. this prevents further writes to th e status register or the f-ram array without another wren command. figure 6 illustrates the wren command bus configuration. wrdi - reset write enable latch the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel is equal to ?0?. figure 7 illustrates the wrdi command bus configuration. figure 4. spi mode 0 figure 5. spi mode 3 table 1. opcode commands name description opcode wren set write enable latch 0000 0110b wrdi reset write enable latch 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b fstrd fast read memory data 0000 1011b write write memory data 0000 0010b sleep enter sleep mode 1011 1001b rdid read device id 1001 1111b lsb msb 76543210 cs sck si 01 2 3 4 5 67 cs sck si 765432 10 lsb msb 01 2 3 4 5 67 figure 6. wren bus configuration figure 7. wrdi bus configuration 0 0 0 0 0 1 1 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 00 1
CY15B102Q document number: 001-89166 rev. *f page 7 of 22 status register and write protection the write protection features of the CY15B102Q are multi-tiered and are enabled through the status register. the status register is organized as follows. (the default value shipped from the factory for bit 0, wel, bp0, bp1, bits 4?5, wpen is ?0?, and for bit 6 is ?1?.) bits 0 and 4-5 are fixed at ?0? and bi t 6 is fixed at ?1?; none of these bits can be modified. note that bit 0 ("ready or write in progress? bit in serial flash and eeprom) is unnecessary, as the f-ram writes in real-time and is never busy, so it reads out as a ?0?. an exception to this is when the device is waking up from sleep mode, which is described in sleep mode on page 10 . the bp1 and bp0 control the software wr ite-protection f eatures and are nonvolatile bits. the wel flag indicates the state of the write enable latch. attemp ting to directly write the wel bit in the status register has no effect on it s state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify portions of me mory that are write- protected as shown in ta b l e 4 . the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memo ry from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the write protect enable bit (wpen) in the status register controls the effect of the hardware write protect (wp ) pin. when the wpen bit is set to '0', the status of the wp pin is ignored. when the wpen bit is set to '1', a low on the wp pin inhibits a write to the status register. thus the status register is write-protected only when wpen = '1' and wp = '0'. ta b l e 5 summarizes the write protection conditions. rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading the status register provides information about the current state of the write-protection features. fo llowing the rdsr opcode, the CY15B102Q will return one byte with the contents of the status register. wrsr - write status register the wrsr command allows the spi bus master to write into the status register and change the write protect configuration by setting the wpen, bp0, and bp1 bits as required. before issuing a wrsr command, the wp pin must be high or inactive. note that on the CY15B102Q, wp only prevents writing to the status register, not the memory array. before sending the wrsr command, the user must send a wren command to enable writes. executing a wrsr command is a write operation and therefore, clears the write enable latch. table 2. status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen (0) x (1) x (0) x (0) bp1 (0) bp0 (0) wel (0) x (0) table 3. status register bit definition bit definition description bit 0 don?t care this bit is non-writable and always returns ?0? upon read. bit 1 (wel) write enable wel indicates if the device is wr ite enabled. this bit defaults to ?0? (disabled) on power-up. wel = '1' --> write enabled wel = '0' --> write disabled bit 2 (bp0) block protect bit ?0? used for block protection. for details, see table 4 on page 7 . bit 3 (bp1) block protect bit ?1? used for block protection. for details, see table 4 on page 7 . bit 4-5 don?t care these bits are non-writable and always return ?0? upon read. bit 6 don?t care this bit is non-writable and always returns ?1? upon read. bit 7 (wpen) write protect enable bit used to ena ble the function of write protect pin (wp ). for details, see table 5 on page 7 . table 4. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 30000h to 3ffffh (upper 1/4) 1 0 20000h to 3ffffh (upper 1/2) 1 1 00000h to 3ffffh (all) table 5. write protection wel wpen wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected
CY15B102Q document number: 001-89166 rev. *f page 8 of 22 memory operation the spi interface, which is capable of a high clock frequency, highlights the fast write capability of the f-ram technology. unlike serial flash and eeproms, the CY15B102Q can perform sequential writes at bus speed. no page register is needed and any number of sequential wr ites may be performed. write operation all writes to the memory begin with a wren opcode with cs being asserted and deasserted. the next opcode is write. the write opcode is followed by a three-byte address containing the 18-bit address (a17-a0) of the first data byte to be written into the memory. the upper six bits of the three-byte address are ignored. subsequent bytes are data bytes, which are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and keeps cs low. if the last address of 3ffffh is reached, the counter will roll over to 00000h. data is written to msb first. the rising edge of cs terminates a write operation. a write operation is shown in figure 10 . note when a burst write reaches a protected block address, the automatic address increment stops and all the subsequent data bytes received for write will be ignored by the device. eeproms use page buffers to increase their write throughput. this compensates for the technology's inherently slow write operations. f-ram memories do not have page buffers because each byte is written to the f-ram array immediately after it is clocked in (after the eighth cl ock). this allows any number of bytes to be written without page buffer delays. note if the power is lost in the mi ddle of the write operation, only the last completed byte will be written. read operation after the falling edge of cs , the bus master can issue a read opcode. following the read command is a three-byte address containing the 18-bit address (a17-a 0) of the first byte of the read operation. the upper six bits of the address are ignored. after the opcode and address are issued, the device drives out the read data on the next eight cl ocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addre sses are incremented internally as long as the bus master continues to issue clocks and cs is low. if the last address of 3fff fh is reached, the counter will roll over to 00000h. data is read msb first. the rising edge of cs terminates a read operation and tristates the so pin. a read operation is shown in figure 11 . fast read operation the CY15B102Q supports a fast read opcode (0bh) that is provided for code compatibility with serial flash devices. the fast read opcode is followed by a three-byte address containing the 18-bit address (a17-a 0) of the first byte of the read operation and then a dummy byte. the dummy byte inserts a read latency of the 8-clock cycl e. the fast r ead operation is otherwise the same as an ordinary read operation except that it figure 8. rdsr bus configuration figure 9. wrsr bus configuration (wren not shown) cs sck so 01234567 si 000001 0 0 1 hi-z 012345 67 lsb d0 d1 d2 d3 d4 d5 d6 msb d7 opcode data cs sck so 0123 4567 si 00 00000 1 msb lsb d2 d3 d7 hi-z 012345 67 opcode data x x x x x
CY15B102Q document number: 001-89166 rev. *f page 9 of 22 requires an additional dummy byte. after receiving the opcode, address, and a dummy byte, the CY15B102Q starts driving its so line with data bytes, with ms b first, and continues trans- mitting as long as the device is selected and the clock is available. in case of bulk read, the internal address counter is incremented automatically, and afte r the last address 3ffffh is reached, the counter rolls over to 00000h. when the device is driving data on its so line, any tr ansition on its si line is ignored. the rising edge of cs terminates a fast read operation and tristates the so pin. a fast read operation is shown in figure 12 . figure 10. memory write (wren not shown) operation figure 11. memory read operation figure 12. fast read operation ~ ~ cs sck so 01234 5 6 70 7 6 5 4 3 2 1 2021222301234567 msb lsb data d0 d1 d2 d3 d4 d5 d6 d7 si opcode 0000001 x x x x x a17 0 x a16 a3 a1 a2 a0 18-bit address msb lsb hi-z cs sck so 01 23456 70 7 6 5 4 3 2 1 20212223012345 6 7 msb lsb data si opcode 0000001 x x x x x a17 1 x a16 a3 a1 a2 a0 18-bit address msb lsb d0 d1 d2 d3 d4 d5 d6 d7 hi-z cs sck so 012345670 7 6 5 4 3 2 1 202122232425262728 293031 data si opcode 0000101 xxx x a17 1 x a16 a3 a1 a2 a0 18-bit address msb lsb msb lsb d0 d1 d2 d3 d4 d5 d6 d7 012345 67 x x x x x x x x dummy byte hi-z x
CY15B102Q document number: 001-89166 rev. *f page 10 of 22 hold pin operation the hold pin can be used to interrupt a serial operation without aborting it. if the bus master pulls the hold pin low while sck is low, the current operation will pause. taking the hold pin high while sck is low will resume an operation. the transitions of hold must occur while sck is low, but the sck and cs pin can toggle during a hold state. sleep mode a low-power sleep mode is implemented on the CY15B102Q device. the device will enter the low-power state when the sleep opcode b9h is clocked-in and a rising edge of cs is applied. when in sleep mode, the sck and si pins are ignored and so will be hi-z, but the device continues to monitor the cs pin. on the next falling edge of cs , the device will return to normal operation within t rec time. the so pin remains in a hi-z state during the wakeup period. the device does not necessarily respond to an opcode within the wakeup period. to start the wakeup procedure, the controller may send a ?dummy? read, for example, and wait the remaining t rec time. figure 13. hold operation [2] cs sck hold so ~ ~ ~ ~ si valid in valid in figure 14. sleep mode operation cs sck si so hi-z 0 enters sleep mode valid in t su t rec recovers from sleep mode 10111 00 1 1 2 3 4 5 6 7 2. figure 13 shows the hold operation for input mode and output mode.
CY15B102Q document number: 001-89166 rev. *f page 11 of 22 device id the CY15B102Q device can be interrogated for its manufacturer, product identification, and die revision. the rdid opcode 9fh allows the user to read the manufacturer id and product id, both of which are read-only bytes. the jedec-assigned manufacturer id places the cypress (ramtron) identifier in bank 7; therefore, there are six bytes of the continuation code 7fh followed by the single byte c2h. there are two bytes of product id, which includes a family code, a density code, a sub code, and the product revision code. endurance the CY15B102Q devices are capable of being accessed at least 10 13 times, reads or writes. an f-ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f-ram architecture is based on an array of rows and columns of 32k rows of 64-bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. ta b l e 7 shows endurance calculations for a 64-byte repeating loop, whic h includes an opcode, a starting address, and a sequential 64-byte data stream. this causes each byte to experience one en durance cycle through the loop. table 6. device id device id (9 bytes) device id description 71?16 (56 bits) 15?13 (3 bits) 12?8 (5 bits) 7?6 (2 bits) 5?3 (3 bits) 2?0 (3 bits) manufacturer id product id family density sub rev rsvd 7f7f7f7f7f7fc225c8h 0111111101111111011111110111 1111011111110111111111 000010 001 00101 11 001 000 figure 15. read device id cs sck so si opcode ~ ~ 01 2 3 456 70 7 6 5 4 3 2 1 444546 5556575859606162636465666768697071 10011111 lsb msb hi-z 47 48 49 50 51 52 53 54 9-byte device id d7 d6 d5 d4 d3 d2 d1 d0 d3 d1 d7 d2 d0 d5 d3 d1 d4 d2 d7 d5 d3 d6 d4 d6 d0 d1 d7 d5 d0 d6 d3 d1 d2 d0 d2 d4 table 7. time to reach endurance limit for repeating 64-byte loop sck freq (mhz) endurance cycles/sec endurance cycles/year years to reach limit 25 45,950 1.45 10 12 6.91 10 18,380 5.79 10 11 17.27 5 9,190 2.90 10 11 34.5
CY15B102Q document number: 001-89166 rev. *f page 12 of 22 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +150 ? c maximum accumulated storage time at 150 c ambient temperature ................................. 1000 h at 125 c ambient temperature ................................11000 h at 85 c ambient temperature .............................. 121 years ambient temperature with power applied ..... ............... ............... ?55 c to +125 c supply voltage on v dd relative to v ss ........?1.0 v to + 4.5 v input voltage ........... ?1.0 v to +4.5 v and v in < v dd + 1.0 v dc voltage applied to outputs in high-z state .................................... ?0.5 v to v dd + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ................. ?2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount lead soldering temperature (3 seconds) ........ .............. .............. .... + 260 ? c dc output current (1 output at a time, 1s duration) .... 15 ma electrostatic discharge voltage human body model (jedec std jesd22-a114-b) ................ 2 kv charged device model (jedec std jesd22-c101-a) .......... 500 v latch-up current .... .............. .............. .............. ...... > 140 ma operating range range ambient temperature (t a ) v dd automotive-e ?40 ? c to +125 ? c 2.0 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [3] max unit v dd power supply 2.0 3.3 3.6 v i dd v dd supply current f sck = 25 mhz; sck toggling between v dd ? 0.2 v and v ss , other inputs v ss or v dd ? 0.2 v. so = open ??5ma i sb v dd standby current cs = v dd . all other inputs v ss or v dd t a = 25 ? c ? 100 150 ? a t a = 85 ? c? ? 250 ? a t a = 125 ? c? ? 750 ? a i zz sleep mode current cs = v dd . all other inputs v ss or v dd t a = 25 ? c?35 ? a t a = 85 ? c??8 ? a t a = 125 ? c? ? 20 ? a i li input leakage current v ss < v in < v dd ??1 ? a i lo output leakage current v ss < v out < v dd ??1 ? a v ih input high voltage 0.7 v dd ?v dd + 0.3 v v il input low voltage ? 0.3 ? 0.3 v dd v v oh1 output high voltage i oh = ?1 ma, v dd = 2.7 v 2.4 ? ? v v oh2 output high voltage i oh = ?100 ? av dd ? 0.2 ? ? v v ol1 output low voltage i ol = 2 ma, v dd = 2.7 v ? ? 0.4 v v ol2 output low voltage i ol = 150 ? a??0.2v note 3. typical values are at 25 c, v dd = v dd (typ). not 100% tested.
CY15B102Q document number: 001-89166 rev. *f page 13 of 22 ac test conditions input pulse levels .................................10% and 90% of v dd input rise and fall times ...................................................3 ns input and output timing reference levels ................0.5 v dd output load capacitance .............................................. 30 pf data retentio n and endurance parameter description test condition min max unit t dr data retention t a = 125 ? c 11000 ? hours t a = 105 ? c 11 ? years t a = 85 ? c 121 ? years nv c endurance over operating temperature 10 13 ? cycles example of an f-ram li fe time in an aec-q 100 automotive application an application does not operate under a st eady temperature for the entire usage life time of the application. instead, it is of ten expected to operate in multiple temperature environments throughout the application?s usage life time. accordingly, the retention specif ication for f-ram in applications often needs to be calculated cumulati vely. an example calculation for a multi-temperature thermal pro file is given in the following table. temperature t time factor t acceleration factor with respect to tmax a [4] profile factor p profile life time l (p) t1 = 125 ? c t1 = 0.1 a1 = 1 8.33 > 10.46 years t2 = 105 ? c t2 = 0.15 a2 = 8.67 t3 = 85 ? c t3 = 0.25 a3 = 95.68 t4 = 55 ? c t4 = 0.50 a4 = 6074.80 capacitance parameter [5] description test conditions max unit c o output pin capacitance (so) t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) 8 pf c i input pin capacitance 6pf thermal resistance parameter description test conditions 8-pin soic unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and proce- dures for measuring thermal impedance, per eia / jesd51. 114 ? c/w ? jc thermal resistance (junction to case) 40 ? c/w a lt ?? ltmax ?? ------------------------ e ea k ------- 1 t --- 1 tmax --------------- - ? ?? ?? == p 1 t1 a1 ------- t2 a2 ------- t3 a3 ------- t4 a4 ------- +++ ?? ?? ------------------------------------------------------- - = lp ?? pltmax ?? ? = notes 4. where k is the boltzmann constant 8.617 10 -5 ev/k, tmax is the highest temperature specified for the product, and t is any temperature within the f-ram product specification. all temperatures are in kelvin in the equation. 5. this parameter is periodically sampled and not 100% tested.
CY15B102Q document number: 001-89166 rev. *f page 14 of 22 ac switching characteristics over the operating range parameters [6] description v dd = 2.0 v to 3.6 v unit cypress parameter alt. parameter min max f sck ? sck clock frequency 0 25 mhz t ch ? clock high time 18 ? ns t cl ? clock low time 18 ? ns t csu t css chip select setup 12 ? ns t csh t csh chip select hold 12 ? ns t od [7, 8] t hzcs output disable time ? 20 ns t odv t co output data valid time ? 16 ns t oh ? output hold time 0 ? ns t d ? deselect time 60 ? ns t r [9, 10] ? data in rise time ? 50 ns t f [9, 10] ? data in fall time ? 50 ns t su t sd data setup time 8 ? ns t h t hd data hold time 8 ? ns t hs t sh hold setup time 12 ? ns t hh t hh hold hold time 12 ? ns t hz [7, 8] t hhz hold low to hi-z ? 25 ns t lz [8] t hlz hold high to data active ? 25 ns notes 6. test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 10% to 90% of v dd , output loading of the specified i ol /i oh and 30 pf load capacitance shown in ac test conditions . 7. t od and t hz are specified with a load capacitance of 5 pf. transiti on is measured when the outputs enter a high impedance state. 8. characterized but not 100% tested in production. 9. rise and fall times measured between 10% and 90% of waveform.
CY15B102Q document number: 001-89166 rev. *f page 15 of 22 figure 16. synchronous data timing (mode 0) figure 17. hold timing hi-z valid in hi-z cs sck si so t cl t ch t csu t su t h t odv t oh t d t csh t od valid in valid in cs sck hold so t hs t hz t lz t hh t hs t hh ~ ~ ~ ~ si t su valid in valid in
CY15B102Q document number: 001-89166 rev. *f page 16 of 22 power cycle timing over the operating range parameter description min max unit t pu power-up v dd (min) to first access (cs low) 1 ? ms t pd last access (cs high) to power-down (v dd (min)) 0 ? s t vr [11] v dd power-up ramp rate 50 ? s/v t vf [11] v dd power-down ramp rate 100 ? s/v t rec [12] recovery time from sleep mode ? 450 s figure 18. power cycle timing cs ~ ~ ~ ~ t pu t vr t vf v dd v dd(min) t pd v dd(min) notes 11. slope measured at any point on v dd waveform. 12. guaranteed by design. refer to figure 14 for sleep mode recovery timing.
CY15B102Q document number: 001-89166 rev. *f page 17 of 22 ordering code definitions ordering information ordering code package diagram package type operating range CY15B102Q-sxe 001-85261 8-pin soic automotive-e CY15B102Q-sxet 001-85261 8-pin soic all these parts are pb-free. contact your local cypress sales representati ve for availability of these parts. option: blank = standard; t = tape and reel temperature range: e = automotive-e (?40 ? c to +125 ? c) x = pb-free package type: s = 8-pin soic q = spi f-ram density: 102 = 2-mbit voltage: b = 2.0 v to 3.6 v f-ram cypress 15 cy b 102 q s x e t -
CY15B102Q document number: 001-89166 rev. *f page 18 of 22 package diagrams figure 19. 8-pin soic (208 mils) package outline, 001-85261 001-85261 **
CY15B102Q document number: 001-89166 rev. *f page 19 of 22 acronyms document conventions units of measure acronym description cpha clock phase cpol clock polarity eeprom electrically erasable programmable read-only memory eia electronic industries alliance f-ram ferroelectric random access memory i/o input/output jedec joint electron devices engineering council jesd jedec standards lsb least significant bit msb most significant bit rohs restriction of hazardous substances spi serial peripheral interface soic small outline integrated circuit symbol unit of measure c degree celsius hz hertz khz kilohertz k ? kilohm mbit megabit mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt
CY15B102Q document number: 001-89166 rev. *f page 20 of 22 document history page document title: CY15B102Q, 2-mbit (256 k 8) serial (spi ) automotive f-ram document number: 001-89166 rev. ecn no. orig. of change submission date description of change ** 4123153 gvch 09/20/2013 new data sheet. *a 4136685 gvch 10/01/2013 updated pin definitions : added additional information on wp and hold pins (this pin must be tied to v dd if not used). modified description for v dd and v ss pins for clarity. updated memory operation : updated sleep mode : added t rec timing in figure 14 . updated power cycle timing : modified the description for t vr and t vf parameters for clarity. *b 4216165 gvch 01/22/2014 updated features : replaced ?120-year data retention? with ?121-year data retention?. updated functional overview : replaced ?data retention for 120 years? with ?data retention for 121 years?. updated memory operation : updated hold pin operation : added note 2 and referred the same note in figure 13 . updated device id : changed device id (9 bytes) from 7f7f7f7f7f7fc20025h to 7f7f7f7f7f7fc22500h in ta b l e 6 . updated maximum ratings : updated electrostatic discharge voltage: changed ?human body model? from 4 kv to 2 kv. changed ?charged device model? from 1.25 kv to 500 v. changed ?machine model? from 250 v to 200 v. updated dc electrical characteristics : added note 3 and referred the same note in ?typ? column. added values of i sb parameter for 25 ? c and 85 ? c. added values of i zz parameter for 25 ? c and 85 ? c. updated data retention and endurance : changed minimum value of t dr parameter from 120 years to 121 years at test condition 85 ? c. updated title with description from ?example of an aec-q100 automotive f-ram application? to ? example of an f-ram life time in an aec-q100 au- tomotive application ? updated power cycle timing : changed description of t vr parameter from ?v dd power-up slew rate? to ?v dd power-up ramp rate?. changed description of t vf parameter from ?v dd power-down slew rate? to ?v dd power-down ramp rate?.
CY15B102Q document number: 001-89166 rev. *f page 21 of 22 *c 4379377 gvch 05/14/2014 changed datasheet status from ?preliminary to final? updated device id : changed device id (9 bytes) from 7f7f7f7f7f7fc20025h to 7f7f7f7f7f7fc225c8h in ta b l e 6 . maximum ratings : electrostatic discharge voltage removed machine model *d 4462029 zsk 07/31/2014 no technical updates. *e 4884669 zsk / psr 08/14/2015 updated maximum ratings : updated ratings of ?storage temper ature? (replaced ?+125 c? with ?+150 ? c?). removed ?maximum junction temperature?. added ?maximum accumulated storage time?. added ?ambient temperature with power applied?. updated to new template. *f 5688050 aesatmp8 04/19/2017 updated logo and copyright. document history page (continued) document title: CY15B102Q, 2-mbit (256 k 8) serial (spi ) automotive f-ram document number: 001-89166 rev. ecn no. orig. of change submission date description of change
CY15B102Q ? cypress semiconductor corporation, 2013-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. document number: 001-89166 rev. *f revised april 20, 2017 page 22 of 22 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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